A read-only memory (ROM) is a type of memory in which data can be permanently stored, for example, by blowing metallic links during programming thereof. Such type of memory can be conventionally accessed at specific locations to read the programmed contents thereof. A much more versatile type of ROM is the programmable read-only memory (PROM) which can be electrically programmed to store data. Some versions of these devices store data permanently; others, however, can be erased with ultraviolet light or an electrical current.
The construction of a floating gate EEPROM (electrically erasable programmable read only memory) cell is similar to that of a field effect transistor, but additionally includes a floating gate between the control gate conductor and the conduction channel of the transistor. In the case of flash EEPROMs employing hot electron injection for programming, channel hot electrons and avalanche injection electrons are injected into and trapped in the floating gate. This condition increases the threshold voltage of the cell, thereby rendering it cutoff in response to normal read operation voltages. Hence, during reading of a cell so programmed, the cell will remain nonconductive (e.g., "0" state) and thus represent a high impedance between the source and drain. On the other hand, cells which have not been programmed will remain conductive (e.g., "1" state) in response to normal read operating voltages. In this manner, the memory can be programmed.
An abrupt junction is desired in order to have a device with enhanced programmability. On the other hand, a graded junction is necessary for enhanced erasability. To meet these criteria, the cell may be programmed at one junction (e.g., drain/channel junction) and may be erased at the other junction (e.g., source/channel junction).
A split-gate cell for an EEPROM has been previously described by G. Samachisa et al. in "A 128K Flash EEPROM Using Double Polysilicon Technology" (ISSCC 1987, p. 76). In this cell, the floating gate overlies only a portion of the channel and the control gate overlies both the floating gate and the remainder of the channel. In other words, there are two transistors in series between a source and a drain.
An EEPROM cell needs optimized programming as well as erasability. To program the device an abrupt junction is needed so that channel hot electron injection can be optimized. On the other hand, the erase function requires a graded junction with a certain amount of n+region underlapping the floating gate. In prior split-gate structures, however, there is only one junction which is used both for programming as well as for erasing. Since programming requires abrupt junction and erase requires a graded junction, there are two conflicting requirements which must be imposed on prior art split gate structures to make this device work. These conflicting requirements make a very poor tradeoff both for the programming as well as the erase characteristics of the cell since the junction is fabricated so that it is neither graded nor abrupt but rather somewhere in between.
Accordingly, improvements which overcome any or all of the problems are presently desirable.